UPD70F3786GJ-GAE-AX Datasheet, PDF (219/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 6 CLOCK GENERATION FUNCTION
CHAPTER 6 CLOCK GENERATION FUNCTION
6.1 Overview
The following clock generation functions are available.
Main clock oscillator
•
In clock-through mode
fX = 3.0 to 6.25 MHz (fXX = 3.0 to 6.25 MHz)
•
In PLL mode
fX = 3.0 to 6.25 MHz (×8: fXX = 24 to 50 MHz)
Subclock oscillator
•
fXT = 32.768 kHz
Multiply (×8) function by PLL (Phase Locked Loop)
•
Clock-through mode/PLL mode selectable
Internal oscillator
•
fR = 220 kHz (TYP.)
Internal system clock generation
•
7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
Peripheral clock generation
Clock output function
Remark
fX: Main clock oscillation frequency
fXX: Main clock frequency
fXT: Subclock frequency
fR: Internal oscillation clock frequency
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 219 of 1817