UPD70F3786GJ-GAE-AX Datasheet, PDF (794/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
(8) Receive operation in FIFO mode (pointer mode specified)
If the pointer mode is specified in the FIFO mode and if as many data as the number of bytes stored in receive
FIFO are read by referencing the UBnFIS0 register, no data may be stored in receive FIFO (UBnFIS0.UBnRB4 to
UBnFIS0.UBnRB0 bits = 00000) even though the reception end interrupt request signal (INTUBnTIR) has
occurred. In this case, do not read data from receive FIFO. Be sure to read data from receive FIFO after
confirming that the number of bytes stored in receive FIFO = 1 byte or more (UBnRB4 to UBnRB0 bits = other
than 00000).
Remark n = 0, 1
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 794 of 1817