UPD70F3786GJ-GAE-AX Datasheet, PDF (381/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
each time the valid edge of the external event count input is detected. Additionally, the set value of the TABnCCR0 register
is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, and a compare match interrupt request signal (INTTABnCC0) is generated.
The INTTABnCC0 signal is generated each time the valid edge of the external event count input has been detected (set
value of TABnCCR0 register + 1) times.
Figure 8-11. Register Setting for Operation in External Event Count Mode (1/2)
(a) TABn control register 0 (TABnCTL0)
TABnCE
TABnCTL0 0/1
0
0
0
TABnCKS2 TABnCKS1 TABnCKS0
0
0
0
0
0: Stop counting
1: Enable counting
(b) TABn control register 1 (TABnCTL1)
TABnSYE TABnEST TABnEEE
TABnCTL1
0
0
0
0
TABnMD2 TABnMD1 TABnMD0
0
0
0
1
0, 0, 1:
External event count mode
(c) TABn I/O control register 0 (TABnIOC0)
TABnOL3 TABnOE3 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0
TABnIOC0
0
0
0
0
0
0
0
0
0: Disable TOABn0 pin output
0: Disable TOABn1 pin output
0: Disable TOABn2 pin output
0: Disable TOABn3 pin output
(d) TABn I/O control register 2 (TABnIOC2)
TABnEES1 TABnEES0 TABnETS1 TABnETS0
TABnIOC2
0
0
0
0
0/1
0/1
0
0
Remark n = 0, 1
Select valid edge
of external event
count input
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 381 of 1817