UPD70F3786GJ-GAE-AX Datasheet, PDF (200/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 5 BUS CONTROL FUNCTION
5.4 Bus Access
5.4.1 Number of clocks for access
The following table shows the number of basic clocks required for accessing each resource.
Bus Cycle Type
Area (Bus Width) Internal ROM (32 Bits)
Instruction fetch (normal access)
1
Instruction fetch (branch)
3
Operand data access
5
Note Increases by 1 if a conflict with a data access occurs.
Internal RAM (32 Bits)
1^Note
2^Note
1
External Memory (16 Bits)
Multiplexed Separate
3+n
3+n
3+n
Remark Unit: Clocks/access
5.4.2 Bus size setting function
Each external memory area selected by memory block CSn can be set by using the BSC register. However, the bus
size can be set to 8 bits and 16 bits only.
The external memory area of the V850ES/JH3-E is selected by using CS0 and CS2, and the external memory area of
the V850ES/JJ3-E is selected by using CS0, CS2 and CS3.
(1) Bus size configuration register (BSC)
The BSC register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access
an external memory area until the initial settings of the BSC register are complete.
After reset: 5555H R/W Address: FFFFF066H
15
14
13
12
11
10
9
BSC
0
1
0
1
0
1
0
7
6
5
4
3
2
1
0
BS30^Note
0
BS20
0
1
0
CS3
CS2
BSn0
0
1
Data bus width of memory block CSn space (n = 0, 2, 3)
8 bits
16 bits
8
1
0
BS00
CS0
Note V850ES/JJ3-E only. Be sure to set this bit to 1 in the V850ES/JH3-E.
Caution Be sure to set bits 14, 12, 10, 8, and 2 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to “0”.
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 200 of 1817