UPD70F3786GJ-GAE-AX Datasheet, PDF (1610/1817 Pages) Renesas Technology Corp – RENESAS MCU V850ES/Jx3-E Microcontrollers

V850ES/JH3-E, V850ES/JJ3-E
CHAPTER 27 STANDBY FUNCTION
27.3 HALT Mode
27.3.1 Setting and operation status
The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode.
In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to
the other on-chip peripheral functions continues.
As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set.
The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating.
Table 27-3 shows the operating status in the HALT mode.
The average current consumption of the system can be reduced by using the HALT mode in combination with the
normal operation mode for intermittent operation.
Cautions 1. Insert five or more NOP instructions after the HALT instruction.
2. If the HALT instruction is executed while an unmasked interrupt request signal is being held
pending, the status shifts to HALT mode, but the HALT mode is then released immediately by the
pending interrupt request.
27.3.2 Releasing HALT mode
The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked
external interrupt request signal (INTPn pin input), unmasked internal interrupt request signal from a peripheral function
operable in the HALT mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or
clock monitor (CLM)).
After the HALT mode has been released, the normal operation mode is restored.
Remark n = 00 to 20: V850ES/JH3-E
n = 00 to 25: V850ES/JJ3-E
(1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request
signal
The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the HALT mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is
issued, the HALT mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is
issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt
request signal is acknowledged.
Table 27-2. Operation After Releasing HALT Mode by Interrupt Request Signal
Release Source
Non-maskable interrupt request
signal
Maskable interrupt request signal
Interrupt Enabled (EI) Status
Execution branches to the handler address.
Execution branches to the handler address
or the next instruction is executed.
Interrupt Disabled (DI) Status
The next instruction is executed.
R01UH0290EJ0300 Rev.3.00
Sep 19, 2011
Page 1610 of 1817