HD6473887 Datasheet, PDF (85/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.3.2 Interrupt Control Registers
Table 3-3 lists the registers that control interrupts.
Table 3-3 Interrupt Control Registers
Name
Abbreviation R/W
IRQ edge select register
IEGR
R/W
Interrupt enable register 1
IENR1
R/W
Interrupt enable register 2
IENR2
R/W
Interrupt request register 1
IRR1
R/W*
Interrupt request register 2
IRR2
R/W*
Wakeup interrupt request register
IWPR
R/W*
Wakeup edge select register
WEGR
R/W
Note: * Write is enabled only for writing of 0 to clear a flag.
Initial Value
H'E0
H'00
H'00
H'20
H'00
H'00
H'00
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF6
H'FFF7
H'FFF9
H'FF90
1. IRQ edge select register (IEGR)
Bit
7
6
5
—
—
—
Initial value
1
1
1
Read/Write
—
—
—
4
IEG4
0
R/W
3
IEG3
0
R/W
2
IEG2
0
R/W
1
IEG1
0
R/W
0
IEG0
0
R/W
IEGR is an 8-bit read/write register used to designate whether pins IRQ₄ to IRQ₀ are set to rising
edge sensing or falling edge sensing.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
Bit 4: IRQ₄ edge select (IEG4)
Bit 4 selects the input sensing of the IRQ₄ pin and ADTRG pin.
Bit 4
IEG4
0
1
Description
Falling edge of IRQ₄ and ADTRG pin input is detected
Rising edge of IRQ₄ and ADTRG pin input is detected
(initial value)
68