HD6473887 Datasheet, PDF (310/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

c. Interrupts and continuous transmission/reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10-13.
Table 10-13 Transmit/Receive Interrupts
Interrupt Flags
RXI
RDRF
RIE
TXI
TDRE
TIE
TEI
TEND
TEIE
Interrupt Request Conditions
Notes
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10-7 (a).)
The RXI interrupt routine reads the
receive data transferred to RDR
and clears bit RDRF to 0.
Continuous reception can be
performed by repeating the above
operations until reception of the
next RSR data is completed.
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10-7 (b).)
The TXI interrupt routine writes the
next transmit data to TDR and
clears bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations
until the data transferred to TSR
has been transmitted.
When the last bit of the character in TSR TEI indicates that the next transmit
is transmitted, if bit TDRE is set to 1, bit data has not been written to TDR
TEND is set to 1. If bit TEIE is set to 1 at when the last bit of the transmit
this time, TEI is enabled and an interrupt character in TSR is sent.
is requested. (See figure 10-7 (c).)
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