HD6473887 Datasheet, PDF (301/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Notes: 1. The setting should be made so that the error is not more than 1%.
2. The value set in BRR is given by the following equation:
N=
OSC
—1
(64 × 2²ⁿ × B)
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 N 255)
OSC: Value of ø_OSC (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10-7.)
Table 10-7 Relation between n and Clock
SMR Setting
n Clock
CKS1
CKS0
0ø
0
0
0
ø_W/2*¹/ø_W*²
0
1
2 ø/16
1
0
3 ø/64
1
1
Notes: 1. ø_W/2 clock is selected in active (medium- and high-speed) or sleep
(medium- and high-speed) mode.
2. ø_W clock is selected in subactive or subsleep mode. SCI3 can be used only
when the ø_W/2 is selected as the CPU clock in subactive or subsleep mode.
3. The error in table 10-6 is the value obtained from the following equation, rounded to two
decimal places.
Error (%) = ^{B (rate obtained from n, N, OSC) — R (bit rate in left-hand column in table 10-6.)} × 100
R (bit rate in left-hand column in table 10-6.)
Table 10-8 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10-8 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz)
Maximum Bit Rate (bit/s)
n
N
0.0384*
600
0
0
2
31250
0
0
2.4576
38400
0
0
4
62500
0
0
Note: * When SMR is set up to CKS1 = “0”, CKS0 = “1”.
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