HD6473887 Datasheet, PDF (317/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD3x pin using the relevant data transfer format in table 10-
14. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers
data from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame.
If bit TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted,
is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10-12 shows an example of the operation when transmitting in asynchronous mode.
Serial
data
Start
bit
Transmit Parity Stop Start
data
bit bit bit
Transmit Parity Stop
data
bit bit
1 0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 1
1 frame
1 frame
Mark
state
1
TDRE
TEND
LSI
TXI request
operation
User
processing
TDRE
cleared to 0
Data written
to TDR
TXI request
TEI request
Figure 10-12 Example of Operation when Transmitting in Asynchronous Mode
(8-bit data, parity, 1 stop bit)
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