HD6473887 Datasheet, PDF (259/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

4. Register configuration
Table 9-20 shows the register configuration of the asynchronous event counter.
Table 9-20 Asynchronous Event Counter Registers
Name
Abbrev. R/W
Event counter control/status register ECCSR
R/W
Event counter H
ECH
R
Event counter L
ECL
R
Clock stop register 2
CKSTP2 R/W
Initial Value
H'00
H'00
H'00
H'FF
Address
H'FF95
H'FF96
H'FF97
H'FFFB
9.7.2 Register Descriptions
1. Event counter control/status register (ECCSR)
Bit
7
6
5
4
3
OVH
OVL
—
CH2
CUEH
Initial Value
0
0
0
0
0
Read/Write
R/(W)* R/(W)*
R/W
R/W
R/W
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
2
CUEL
0
R/W
1
CRCH
0
R/W
0
CRCL
0
R/W
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
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