HD6473887 Datasheet, PDF (256/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Figure 9-17 shows an example of watchdog timer operations.
Example: ø = 2 MHz and the desired overflow period is 30 ms.
2 × 10⁶
8192
× 30 × 10^–3 = 7.3
The value set in TCW should therefore be 256 – 8 = 248 (H'F8).
H'FF
H'F8
TCW count
value
TCW overflow
H'00
Internal reset
signal
Start
H'F8 written
in TCW
H'F8 written in TCW
Reset
512 ø_OSC clock cycles
Figure 9-17 Typical Watchdog Timer Operations (Example)
9.6.4 Watchdog Timer Operation States
Table 9-18 summarizes the watchdog timer operation states.
Table 9-18 Watchdog Timer Operation States
Operation
Mode
Reset
Active Sleep
Watch
Module
Subactive Subsleep Standby Standby
TCW
Reset
Functions Functions Halted
Functions/ Halted
Halted*
Halted
Halted
TCSRW
Reset
Functions Functions Retained Functions/ Retained
Halted*
Note: * Functions when øw/32 is selected as the input clock.
Retained
Retained
239