HD6473887 Datasheet, PDF (19/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 1-1 Features
Item
CPU
Interrupts
Clock pulse
generators
Power-down
modes
Description
High-speed H8/300L CPU
• General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
• Operating speed
 Max. operating speed: 3 Mhz
 Add/subtract: 0.67 µs (operating at 3 Mhz)
 Multiply/divide: 4.67 µs (operating at 3 Mhz)
 Can run on 32.768 kHz or 38.4 kHz subclock
• Instruction set compatible with H8/300 CPU
 Instruction length of 2 bytes or 4 bytes
 Basic arithmetic operations between registers
 MOV instruction for data transfer between memory and registers
• Typical instructions
 Multiply (8 bits × 8 bits)
 Divide (16 bits ÷ 8 bits)
 Bit accumulator
 Register-indirect designation of bit position
37 interrupt sources
• 13 external interrupt sources (IRQ4 to IRQ0, WKP7 to WKP0)
• 24 internal interrupt sources
Two on-chip clock pulse generators
• System clock pulse generator: 0.4 to 6 Mhz
• Subclock pulse generator: 32.768 kHz, 38.4 kHz
Seven power-down modes
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
• Standby mode
• Watch mode
• Subsleep mode
• Subactive mode
• Active (medium-speed) mode
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