HD6473887 Datasheet, PDF (293/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit 7: Transmit interrupt enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7
TIE
0
1
Description
Transmit data empty interrupt request (TXI) disabled
Transmit data empty interrupt request (TXI) enabled
(initial value)
Bit 6: Receive interrupt enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive error: overrun, framing, and parity.
RXI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing
bit RIE to 0.
Bit 6
RIE
0
1
Description
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
(initial value)
Bit 5: Transmit enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE
Description
0
Transmit operation disabled*¹ (TXD pin is I/O port)
(initial value)
1
Transmit operation enabled*² (TXD pin is transmit data pin)
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC31 or SPC32 in SPCR, to decide the transmission format
before setting bit TE to 1.
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