HD6473887 Datasheet, PDF (353/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bits 3 to 0: Channel select (CH3 to CH0)
Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3
CH3
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 2
CH2
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
CH1
*
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
CH0
*
0
1
0
1
0
1
0
1
0
1
0
1
Analog Input Channel
No channel selected
AN₀
AN₁
AN₂
AN₃
AN₄
AN₅
AN₆
AN₇
AN₈
AN₉
AN ₁₀
AN ₁₁
(initial value)
*: Don’t care
12.2.3 A/D Start Register (ADSR)
Bit
7
6
5
4
3
2
1
0
ADSF
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated
edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the
converted data is set in ADRRH and ADRRL, and at the same time ADSF is cleared to 0.
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