HD6473887 Datasheet, PDF (357/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12-4 and 12-5 show flow charts of procedures for using the A/D converter.
Interrupt
(IRRAD)
IENAD
ADSF
Set *
Set *
A/D conversion starts
Set *
Channel 1 (AN₁)
operation state
Idle
A/D conversion (1)
Idle
A/D conversion (2)
ADRRH
ADRRL
Note: * ( ) indicates instruction execution by software.
Read conversion result
A/D conversion result (1)
Idle
Read conversion result
A/D conversion result (2)
Figure 12-3 Typical A/D Converter Operation Timing
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