HD6473887 Datasheet, PDF (443/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

SSR31—Serial status register31
H'9C
SCI3
Bit
Initial value
Read/Write
7
6
5
TDRE31 RDRF31 OER31
1
0
0
R/(W)^* R/(W)^* R/(W)^*
4
FER31
0
R/(W)^*
3
2
1
0
PER31 TEND31 MPBR31 MPBT31
0
1
R/(W)^*
R
0
0
R
R/W
Multiprocessor bit transfer
0 A 0 multiprocessor bit is transmitted
1 A 1 multiprocessor bit is transmitted
Multiprocessor bit receive
0 Data in which the multiprocessor bit is 0 has been received
1 Data in which the multiprocessor bit is 1 has been received
Transmit end
0 Transmission in progress
[Clearing conditions] • After reading TDRE31 = 1, cleared by writing 0 to TDRE
• When data is written to TDR31 by an instruction
1 Transmission ended
[Setting conditions] • When bit TE in serial control register 31 (SCR31) is cleared to 0
• When bit TDRE31 is set to 1 when the last bit of a transmit character is sent
Parity error
0 Reception in progress or completed normally
[Clearing conditions] After reading PER31 = 1, cleared by writing 0 to PER31
1 A parity error has occurred during reception
[Setting conditions] When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM31) in the serial mode register (SMR31)
Framing error
0 Reception in progress or completed normally
[Clearing conditions] After reading FER31 = 1, cleared by writing 0 to FER31
1 A framing error has occurred during reception
[Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun error
0 Reception in progress or completed
[Clearing conditions] After reading OER31 = 1, cleared by writing 0 to OER31
1 An overrun error has occurred during reception
[Setting conditions] When the next serial reception is completed with RDRF31 set to 1
Receive data register full
0 There is no receive data in RDR31
[Clearing conditions] • After reading RDRF31 = 1, cleared by writing 0 to RDRF31
• When RDR31 data is read by an instruction
1 There is receive data in RDR31
[Setting conditions] When reception ends normally and receive data is transferred from RSR31 to RDR31
Transmit data register empty
0 Transmit data written in TDR31 has not been transferred to TSR31
[Clearing conditions] • After reading TDRE31 = 1, cleared by writing 0 to TDRE31
• When data is written to TDR31 by an instruction
1 Transmit data has not been written to TDR31, or transmit data written in TDR31 has been transferred to TSR31
[Setting conditions] • When bit TE in serial control register 31 (SCR31) is cleared to 0
• When data is transferred from TDR31 to TSR31
Note: * Only a write of 0 for flag clearing is possible.
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