HD6473887 Datasheet, PDF (329/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Sender
Communication line
Receiver A
(ID = 01)
Receiver B
(ID = 02)
Receiver C
(ID = 03)
Receiver D
(ID = 04)
Serial
data
H'01
(MPB = 1)
H'AA
(MPB = 0)
ID transmission cycle
Data transmission cycle
(specifying the receiver) (sending data to the receiver
specified buy the ID)
MPB: Multiprocessor bit
Figure 10-21 Example of Inter-Processor Communication Using Multiprocessor Format
(Sending data H'AA to receiver A)
There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity
bit specification is invalid. See table 10-14 for details.
For details on the clock used in multiprocessor communication, see 10.3.3, 2. Operation in
Asynchronous Mode.
• Multiprocessor transmitting
Figure 10-22 shows an example of a flowchart for multiprocessor data transmission. This
procedure should be followed for multiprocessor data transmission after initializing SCI3.
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