HD6473887 Datasheet, PDF (237/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit 5: Timer overflow interrupt enable (OVIE)
Bit 5 selects enabling or disabling of interrupt generation when TCG overflows.
Bit 5
OVIE
0
1
Description
TCG overflow interrupt request is disabled
TCG overflow interrupt request is enabled
(initial value)
Bit 4: Input capture interrupt edge select (IIEGS)
Bit 4 selects the input capture input signal edge that generates an interrupt request.
Bit 4
IIEGS
0
1
Description
Interrupt generated on rising edge of input capture input signal
Interrupt generated on falling edge of input capture input signal
(initial value)
Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
CCLR1
0
0
1
1
Bit 2
CCLR0
0
1
0
1
Description
TCG clearing is disabled
TCG cleared by falling edge of input capture input signal
TCG cleared by rising edge of input capture input signal
TCG cleared by both edges of input capture input signal
(initial value)
Bits 1 and 0: Clock select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Bit 1
CKS1
0
0
1
1
Bit 0
CKS0
0
1
0
1
Description
Internal clock: counting on ø/64
Internal clock: counting on ø/32
Internal clock: counting on ø/2
Internal clock: counting on øw/4
(initial value)
220