HD6473887 Datasheet, PDF (461/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

TMG—Timer mode register G
H'BC
Bit
Initial value
Read/Write
7
OVFH
0
R/(W)*
6
OVFL
0
R/(W)*
5
OVIE
0
W
4
IIEGS
0
W
3
CCLR1
0
W
2
CCLR0
0
W
1
CKS1
0
W
0
CKS0
0
W
Timer G
Clock select
0 0 Internal clock: counting on ø/64
0 1 Internal clock: counting on ø/32
1 0 Internal clock: counting on ø/2
Counter clear
1 1 Internal clock: counting on øw/4
00
01
10
11
TCG clearing is disabled
TCG cleared by falling edge of input capture input signal
TCG cleared by rising edge of input capture input signal
TCG cleared by both edges of input capture input signal
Input capture interrupt edge select
0 Interrupt generated on rising edge of input capture input signal
1 Interrupt generated on falling edge of input capture input signal
Timer overflow interrupt enable
0 TCG overflow interrupt request is disabled
1 TCG overflow interrupt request is enabled
Timer overflow flag L
0 Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
1 Setting conditions:
Set when TCG overflows from H'FF to H'00
Timer overflow flag H
0 Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1 Setting conditions:
Set when TCG overflows from H'FF to H'00
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
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