HD6473887 Datasheet, PDF (295/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit 2: Transmit end interrupt enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
Description
0
Transmit end interrupt request (TEI) disabled
(initial value)
1
Transmit end interrupt request (TEI) enabled*
Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
Bits 1 and 0: Clock enable 1 and 0 (CKE1, CKE0)
Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK_3X pin.
The combination of CKE1 and CKE0 determines whether the SCK_3X pin functions as an I/O port,
a clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10-4 in 10.1.3, Operation.
Bit 1
Bit 0
Description
CKE1 CKE0 Communication Mode
Clock Source
0
0
Asynchronous
Internal clock
Synchronous
Internal clock
0
1
Asynchronous
Internal clock
Synchronous
Reserved
1
0
Asynchronous
External clock
Synchronous
External clock
1
1
Asynchronous
Reserved
Synchronous
Reserved
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
SCK_3X Pin Function
I/O port*¹
Serial clock output*¹
Clock output*²
Clock input*³
Serial clock input
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