HD6473887 Datasheet, PDF (221/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

4. Timer control/status register F (TCSRF)
Bit:
Initial value:
Read/Write:
7
OVFH
0
R/(W)*
6
CMFH
0
R/(W)*
5
OVIEH
0
R/W
4
CCLRH
0
R/W
3
OVFL
0
R/(W)*
2
CMFL
0
R/(W)*
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
1
OVIEL
0
R/W
0
CCLRL
0
R/W
TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH
0
1
Description
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
Setting conditions:
Set when TCFH overflows from H'FF to H'00
(initial value)
Bit 6: Compare match flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH
0
1
Description
Clearing conditions:
After reading CMFH = 1, cleared by writing 0 to CMFH
Setting conditions:
Set when the TCFH value matches the OCRFH value
(initial value)
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