HD6473887 Datasheet, PDF (437/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

ECCSR—Event counter control/status register
H'95
AEC
Bit
Initial value
Read/Write
7
6
5
OVH OVL
—
0
0
0
R/(W)* R/(W)* R/W
4
CH2
0
R/W
3
CUEH
0
R/W
2
CUEL
0
R/W
1
CRCH
0
R/W
0
CRCL
0
R/W
Counter reset control L
0 ECL is reset
1 ECL reset is cleared
and count-up function
is enabled
Counter reset control H
0 ECH is reset
1 ECH reset is cleared and
count-up function is enabled
Count-up enable L
0 ECL event clock input is disabled.
ECL value is held
1 ECL event clock input is enabled
Count-up enable H
0 ECH event clock input is disabled.
ECH value is held
1 ECH event clock input is enabled
Channel select
0 ECH and ECL are used together as a single-
channel 16-bit event counter
1 ECH and ECL are used as two independent
8-bit event counter channels
Counter overflow L
0 ECL has not overflowed
1 ECL has overflowed
Counter overflow H
0 ECH has not overflowed
1 ECH has overflowed
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