HD6473887 Datasheet, PDF (250/523 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

9.6 Watchdog Timer
9.6.1 Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally.
1. Features
Features of the watchdog timer are given below.
• Incremented by internal clock source (ø/8192 or øw/32).
• A reset signal is generated when the counter overflows. The overflow period can be set from
from 1 to 256 times 8192/ø or 32/øw (from approximately 4 ms to 1000 ms when ø = 2.00
MHz).
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
2. Block diagram
Figure 9-16 shows a block diagram of the watchdog timer.
øw/32
ø
PSS
ø/8192
TCSRW
TCW
Notation:
TCSRW: Timer control/status register W
TCW: Timer counter W
PSS: Prescaler S
Figure 9-16 Block Diagram of Watchdog Timer
Reset signal
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