RX71M_15 Datasheet, PDF (8/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
1. Overview
Table 1.1
Outline of Specifications (7/10)
Classification
Communication
function
Module/Function
I²C bus interface
(RIICa)
CAN module (CAN)
Serial peripheral
interface (RSPIa)
Quad serial peripheral
interface (QSPI)
Serial sound interface (SSI)
Sampling rate converter (SRC)
SD host interface (SDHI)*⁴
MMC host interface (MMCIF)
Description
 2 channels (only channel 0 can be used in fast-mode plus)
Communication formats
I²C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 1 Mbps (channel 0)
 Event linking by the ELC
 3 channels
 Compliance with the ISO11898-1 specification (standard frame and extended frame)
 32 mailboxes per channel
 2 channels
 RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
 Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
 Buffered structure
Double buffers for both transmission and reception
 RSPCK can be stopped with the receive buffer full for master reception.
 Event linking by the ELC
 1 channel
 Connectable with serial flash memory equipped with multiple input and output lines (i.e.
for single, dual, or quad operation)
 Programmable bit length and selectable active sense and phase of the clock signal
 Sequential execution of transfer
 LSB or MSB first is selectable.
 2 channels
 Full-duplex transfer is possible (only on channel 0).
 Support for multiple audio formats
 Support for master or slave operation
 Bit clock frequency is selectable from four different types (16 fs, 32 fs, 48 fs, and 64 fs).
 Support for 8-/16-/18-/20-/22-/24 bit data formats
 Internal 8-stage FIFO for transmission and reception
 Stopping SSIWS when data transfer is stopped is selectable.
 1 channel
 Data formats: 32-bit stereo (16 bits for the left, 16 bits for the right) and 16-bit monaural.
 Input sampling rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz
 Output sampling rates: 32, 44.1, 48, 8*² or 16 kHz*²
 1 channel
 One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses)
 SD specifications
Part 1: Physical Layer Specification Ver.3.01 compliant (DDR not supported)
Part E1: SDIO Specification Ver. 3.00
 Error checking: CRC7 for commands and CRC16 for data
 Interrupt requests: Card access interrupt, SDIO access interrupt, card detection
interrupt
 DMA transfer requests: SD_BUF write and SD_BUF read
 Support for card detection and write protection
 1 channel
 Compliant with JEDEC STANDARD JESD84-A441 (DDR is not supported)
 Interface for Multimedia Cards (MMCs)
 Device buses: Support for 1-, 4-, and 8-bit MMC buses
 Interrupt requests: Card detection interrupt, error/timeout interrupt, normal operation
interrupt
 DMA transfer requests: CE_DATA write and CE_DATA read
 Support for card detection, boot operation, high priority interrupt (HPI)
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
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