RX71M_15 Datasheet, PDF (7/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
1. Overview
Table 1.1
Outline of Specifications (6/10)
Classification
Communication
function
Module/Function
Ethernet controller
(ETHERC)
PTP controller for
Ethernet controller
(EPTPCa)
DMA controller for
Ethernet controller
(EDMACa)
USB 2.0 FS host/
function module (USBb)
USB 2.0 HS host/
function module with
battery charging
(USBAa)
Serial communications
interfaces (SCIg, SCIh)
Serial communications
interface with FIFO
(SCIFA)
Description
 2 channels
 Input and output of Ethernet/IEEE 802.3 frames
 Transfer at 10 or 100 Mbps
 Full- and half-duplex modes
 MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
 Detection of Magic Packets^TM*¹ or output of a "wake-on-LAN" signal (WOL)
 Compliance with flow control as defined in IEEE 802.3x standards
 Filtering of multicast frames
 Direct transfer of frames between two channels by cut-through
 A block compatible with the IEEE 1588 standard is connected to the Ethernet controller
(ETHERC).
 Matching with a time stamp can start counting by MTU3 and the GPT.
 3 channels (the round-robin method determines the priority of the channels)
2 channels for ETHERC; 1 channel for EPTPC
 Alleviation of CPU load by the descriptor control method
 Transmission FIFO: 2 Kbytes; Reception FIFO: 4 Kbytes
 Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS
 One port
 Compliance with the USB 2.0 specification
 Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)
 Self-power mode and bus power are selectable
 OTG (On the Go) operation is possible (low-speed is not supported)
 Incorporates 2 Kbytes of RAM as a transfer buffer
 External pull-up and pull-down resistors are not required
 Includes a UDC (USB Device Controller) and transceiver for USB 2.0 HS
 One port (only in 177-/176-pin devices)
 Compliance with the USB 2.0 specification
 Transfer rate: High speed (480 Mbps), full speed (12 Mbps),
low speed (1.5 Mbps) (host only)
 Self-power mode and bus power are selectable
 OTG (On the Go) operation is possible (low-speed is not supported)
 Incorporates 8.5 Kbytes of RAM as a transfer buffer
 External pull-up and pull-down resistors are not required
 9 channels (SCIg: 8 channels + SCIh: 1 channel)
 SCIg
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Start-bit detection: Level or edge detection is selectable.
Simple I²C
Simple SPI
9-bit transfer mode
Bit rate modulation
Double-speed mode
Event linking by the ELC (only on chanel 5)
 SCIh (The following functions are added to SCIg)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
 4 channels
 Methods of transfer: Asynchronous and clock synchronous
 Desired bit rates can be selected from the internal baud rate generators.
 LSB or MSB first is selectable.
 Both the transmission and reception sections are equipped with 16-byte FIFO buffers,
allowing continuous transmission and reception.
 Bit rate modulation
 Double-speed mode
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 7 of 228