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RX71M_15 Datasheet, PDF (180/228 Pages) Renesas Technology Corp – Renesas MCUs
RX71M Group
5. Electrical Characteristics
Table 5.32 SCI and SCIF Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
Symbol
SCI
SCIF
Input clock cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time
Receive data setup time
Receive data hold time
Input clock cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time
Receive data setup time
Receive data hold time
Asynchronous
Clock
synchronous
Asynchronous*2
Clock
synchronous
Clock
synchronous
Clock
synchronous
Clock
synchronous
Asynchronous
Clock
synchronous
Asynchronous*3
Clock
synchronous
Master
Slave
Master
Slave
Master
Slave
tScyc
tSCKW
tSCKr
tSCKf
tScyc
tSCKW
tSCKr
tSCKf
tTXD
tRXS
tRXH
tScyc
tSCKW
tSCKr
tSCKf
tScyc
tSCKW
tSCKr
tSCKf
tTXD
tRXS
tRXH
Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle
Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1
Note 3. When the SEMR.ABCS0 and SEMR.BGDM bits are set to 1
Min.*1
4
6
0.4
—
—
8
4
0.4
—
—
—
15
5
4
12
0.4
—
—
8
4
0.4
—
—
—
—
3 × tPAcyc + 20
tPAcyc + 10
–3 × tPAcyc + 5
2 × tPAcyc + 10
Max.*1
—
—
0.6
5
5
—
—
0.6
5
5
28
—
—
—
—
0.6
5
5
—
—
0.6
5
5
10
4 × tPAcyc + 20
—
—
—
—
Unit*1
Test
Conditions
tPBcyc Figure 5.44
tScyc
ns
ns
tPBcyc
tScyc
ns
ns
ns
Figure 5.45
ns
ns
tPAcyc Figure 5.44
tScyc
ns
ns
tPAcyc
tScyc
ns
ns
ns
Figure 5.45
ns
ns
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 180 of 228