RX71M_15 Datasheet, PDF (10/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
1. Overview
Table 1.1
Outline of Specifications (9/10)
Classification
Safety
Module/Function
Memory protection unit
(MPU)
Trusted Memory (TM)
Function
Register write
protection function
CRC calculator (CRC)
Encryption
function
Main clock oscillation
stop function
Clock frequency
accuracy measurement
circuit (CAC)
Data operation circuit
(DOC)
AESa*³
DES*³
SHAa*³
True random number
generator (RNG)*³
Operating frequency
Power supply voltage
Operating temperature
Package
Description
 Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to
FFFF FFFFh.
 Minimum protection unit: 16 bytes
 Reading from, writing to, and enabling the execution access can be specified for each
area.
 An address exception occurs when the detected access is not in the permitted area.
 Protects against the reading of programs from blocks 8 and 9 of the code flash memory
 Instruction fetching by the CPU is the only form of access to these areas when the TM
function is enabled.
 Protects important registers from being overwritten for in case a program runs out of
control.
 CRC code generation for arbitrary amounts of data in 8-bit units
 Select any of three generating polynomials:
X⁸ + X² + X + 1, X¹⁶ + X¹⁵ + X² + 1, or X¹⁶ + X¹² + X⁵ + 1
 Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable
 Main clock oscillation stop detection: Available
 Monitors the clock output from the main clock oscillator, sub-clock oscillator, low- and
high-speed on-chip oscillators, the PLL frequency synthesizer, IWDT-dedicated on-chip
oscillator, and PCLKB, and generates interrupts when the setting range is exceeded.
 The function to compare, add, or subtract 16-bit data
 Key lengths: 128, 196, and 256 bits
 Support for CBC, ECB, CFB, OFB, CTR, and CMAC operating modes
 Speed of calculations: 128-bit key length in 22 cycles
192-bit key length in 26 cycles
256-bit key length in 30 cycles
 Compliant with FIPS PUB 197
 Key lengths: 56 bits (DES)/3 × 56 bits (T-DES)
 Support for DES and triple DES
 Support for ECB and CBC operating modes
 Speed of calculations: 6 clock cycles in single DES mode
14 clock cycles in triple DES mode
 Compliant with FIPS PUB 46-3
 Compliant with FIPS PUB 81
 Support for SHA-1 (128), SHA-2 (224 or 256), and HMAC (160, 224, or 256)
 Speed of calculations: 50 clock cycles in SHA-1 mode
42 clock cycles in SHA-224 mode
42 clock cycles in SHA-256 mode
 Compliant with SHA as defined in FIPS PUB 180-1 and -2
 Compliant with HMAC as defined in FIPS PUB 198
 Length of random numbers: 16 bits
 Generation of random-number-generated interrupts after a number is generated
 Random number generation time: 3.6 ms (typ)
Up to 240 MHz
VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7  VREFH0  AVCC0,
VCC_USBA = AVCC_USBA = 2.7 to 3.6 V,
V_BATT = 2.0 to 3.6 V
D-version: 40 to +85°C
G-version: 40 to +105°C (in planning)
177-pin TFLGA (PTLG0177KA-A) (in planning)
176-pin LFBGA (PLBG0176GA-A) (in planning)
176-pin LQFP (PLQP0176KB-A)
145-pin TFLGA (PTLG0145KA-A) (in planning)
144-pin LQFP (PLQP0144KA-A)
100-pin TFLGA (PTLG0100JA-A) (in planning)
100-pin LQFP (PLQP0100KB-A)
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
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