RX71M_15 Datasheet, PDF (158/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
5.3.5
Bus Timing
5. Electrical Characteristics
Table 5.21 Bus Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
ICLK = 8 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
Address delay time
Byte control delay time
CS# delay time
ALE delay time
RD# delay time
Read data setup time
Read data hold time
WR# delay time
Write data delay time
Write data hold time
WAIT# setup time
WAIT# hold time
Address delay time 2 (SDRAM)
CS# delay time 2 (SDRAM)
DQM delay time (SDRAM)
CKE delay time (SDRAM)
Read data setup time 2 (SDRAM)
Read data hold time 2 (SDRAM)
Write data delay time 2 (SDRAM)
Write data hold time 2 (SDRAM)
WE# delay time (SDRAM)
RAS# delay time (SDRAM)
CAS# delay time (SDRAM)
Symbol
t_AD
t_BCD
t_CSD
t_ALED
t_RSD
t_RDS
t_RDH
t_WRD
t_WDD
t_WDH
t_WTS
t_WTH
t_AD2
t_CSD2
t_DQMD
t_CKED
t_RDS2
t_RDH2
t_WDD2
t_WDH2
t_WED
t_RASD
t_CASD
Min.
—
—
—
—
—
12.5
0
—
—
0
12.5
0
1
1
1
1
10
0
—
1
1
1
1
Max.
12.5
12.5
12.5
12.5
12.5
—
—
12.5
12.5
—
—
—
12.5
12.5
12.5
12.5
—
—
12.5
—
12.5
12.5
12.5
Unit
Test Conditions
ns
Figure 5.16 to
ns
Figure 5.21
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.22
ns
ns
Figure 5.23
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 158 of 228