RX71M_15 Datasheet, PDF (143/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
5. Electrical Characteristics
Table 5.4 DC Characteristics (3)
Conditions: VCC = AVCC0 = AVCC1 = VREFH0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
T_a = T_opr
Supply
current*¹
Item
Symbol Min. Typ.
Max.*²
Normal
Peripheral function clock signal
supplied*⁴
I_CC*³
—
—
— 52
Peripheral function clock signal
stopped*⁴
— 28
Coremark Peripheral function clock signal
stopped*⁴
— 41
Sleep mode: The clock signal to peripheral
37
modules is supplied*⁴
All-module-clock-stop mode (reference value)
— 15
Increased
by BGO
operation
*5
Reading from the code flash memory
while the data flash memory is being
programmed
Reading from the code flash memory
while the code flash memory is being
programmed
—
7
— 10
Low-speed operating mode 1: Supply of the clock signal
to peripheral modules is stopped*⁴
— 4.4
Low-speed operating mode 2: Supply of the clock signal
to peripheral modules is stopped*⁴
—
3
Software standby mode
— 1.9
Power supplied to standby RAM and USB resume
detecting unit (USBb only)
— 25
Power not
supplied to
standby RAM and
USB resume
detecting unit
(USBb only)
Power-on reset circuit and low-
power consumption function
disabled*⁶
Power-on reset circuit and low-
power consumption function
enabled*⁷
— 12.5
— 3.1
Increased by
RTC operation
When a crystal oscillator for
low clock loads is in use
— 0.6
When a crystal oscillator for
standard clock loads is in use
— 2.0
RTC operating while
VCC is off (with the
battery backup
function, only the RTC
and sub-clock
oscillator operate)
When a crystal oscillator for
low clock loads is in use
When a crystal oscillator for
standard clock loads is in use
— 0.9
— 1.6
— 1.7
— 3.3
Max.
220
—
—
—
108
80
—
—
—
—
59
75
26
13.5
—
—
—
—
—
—
Unit Test Conditions
mA ICLK = 240 MHz
PCLKA = 120 MHz
PCLKB = 60 MHz
PCLKC = 60 MHz
PCLKD = 60 MHz
FCLK = 60 MHz
BCLK = 120 MHz
BCLK pin = 60 MHz
All clocks 1 MHz
All clocks 32.768 kHz
μA
V_BATT = 2.0 V,
VCC = 0 V
V_BATT = 3.3 V,
VCC = 0 V
V_BATT = 2.0 V,
VCC = 0 V
V_BATT = 3.3 V,
VCC = 0 V
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Supply of the clock signal to peripheral modules is stopped in this state. This does not include operations as BGO (background
operations).
Note 3. I_CC depends on f (ICLK) as follows. (ICLK:PCLKA:PCLKB/PCLKC/PCLKD:BCLK:BCLK pin = 10:5:2.5:5:2.5 when EXTAL = 24
MHz)
I_CC Max. = 0.47 × f + 107 (max. operation in high-speed operating mode)
I_CC Typ. = 0.09 × f + 7 (normal operation in high-speed operating mode)
I_CC Typ. = 0.14 × f + 74 (low-speed operating mode 1)
I_CC Max. = 0.50 × f + 4 (sleep mode)
Note 4. This does not include operations as BGO (background operations). Whether supply of the clock signal to peripheral modules
continues or is stopped only depends on the state determined by the settings of the bits in module stop control registers A to D.
The setting for the peripheral module clock stopped state is FCLK = BCLK = PCLKA = PCLKB = PCLKC = PCLKD = BCLK pin
= 3.75 MHz (division by 64).
Note 5. This is the increase for programming or erasure of the code flash memory (limitations apply to the combinations of ranges in
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 143 of 228