RX71M_15 Datasheet, PDF (154/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
5. Electrical Characteristics
5.3.3
Timing of Recovery from Low Power Consumption Modes
Table 5.18 Timing of Recovery from Low Power Consumption Modes (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
T_a = T_opr
Item
Symbol Min. Typ.
Recovery time Crystal
after
resonator
Main clock
oscillator
t_SBYMC — —
cancellation of connected to operating
software
standby
mode*¹
main clock
oscillator
Main clock
oscillator and
PLL circuit
t_SBYPC
operating
External clock Main clock
input to main oscillator
clock oscillator operating
t_SBYEX
Main clock
oscillator and
PLL circuit
operating
t_SBYPE
Sub-clock oscillator operating t_SBYSC
High-speed
on-chip
oscillator
operating
High-speed
on-chip
oscillator
operating
High-speed
on-chip
oscillator
operating and
PLL circuit
operating
Low-speed on-chip oscillator
operating*⁴
t_SBYHO
t_SBYPH
t_SBYLO
Max.
t_SBYOSCWT*²
t_SBYSEQ*³
Unit
Test
Conditions
{(MSTS[7:0] bit ×
32) + 76} / 0.216
100 μs + 7/f_ICLK + μs Figure 5.12
2n/f_MAIN
{(MSTS[7:0] bit × 100 μs + 7/f_ICLK +
32) + 138} / 0.216
2n/f_PLL
352
100 μs + 7/f_ICLK +
2n/f_EXMAIN
639
100 μs + 7/f_ICLK +
2n/f_PLL
{(SSTS[7:0] bit ×
16384) + 13} /
0.216 + 10/f_FCLK
454
100 μs + 4/f_ICLK +
2n/f_SUB
100 μs + 7/f_ICLK +
2n/f_HOCO
741
100 μs + 7/f_ICLK +
2n/f_PLL
338
100 μs + 7/f_ICLK +
2n/f_LOCO
Note 1.
Note 2.
Note 3.
Note 4.
The time for return after release from software standby is determined by the value obtained by adding the oscillation stabilization
waiting time (t_SBYOSCWTO) and the time required for operations by the software standby release sequencer (t_SBYSEQ).
When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization
waiting time t_SBYOSCWT is selected.
For n, the greatest value is selected from among the internal clock division settings.
This condition applies when f_ICLK:f_FCLK = 1:1, 2:1, or 4:1.
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 154 of 228