RX71M_15 Datasheet, PDF (22/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
1. Overview
Table 1.4
Pin Functions (4/8)
Classifications
Serial communications
interface (SCIg)
Pin Name
I/O
Description
 Asynchronous mode/clock synchronous mode
SCK0 to SCK7
I/O
Input/output pins for the clock
RXD0 to RXD7
Input Input pins for received data
TXD0 to TXD7
Output Output pins for transmitted data
CTS0# to CTS7#
Input Input pins for controlling the start of transmission and reception
RTS0# to RTS7#
 Simple I²C mode
SSCL0 to SSCL7
SSDA0 to SSDA7
 Simple SPI mode
Output Output pins for controlling the start of transmission and
reception
I/O
Input/output pins for the I²C clock
I/O
Input/output pins for the I²C data
SCK0 to SCK7
I/O
Input/output pins for the clock
SMISO0 to SMISO7
I/O
Input/output pins for slave transmission of data
SMOSI0 to SMOSI7
I/O
Input/output pins for master transmission of data
Serial communications
interface (SCIh)
SS0# to SS7#
Input Chip-select input pins
 Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for the clock
RXD12
Input Input pin for received data
TXD12
Output Output pin for transmitted data
CTS12#
Input Input pin for controlling the start of transmission and reception
RTS12#
 Simple I²C mode
SSCL12
SSDA12
 Simple SPI mode
SCK12
Output Output pin for controlling the start of transmission and reception
I/O
Input/output pin for the I²C clock
I/O
Input/output pin for the I²C data
I/O
Input/output pin for the clock
SMISO12
SMOSI12
I/O
Input/output pin for slave transmission of data
I/O
Input/output pin for master transmission of data
SS12#
 Extended serial mode
Input Chip-select input pin
RXDX12
Input Input pin for received data
TXDX12
Output Output pin for transmitted data
SIOX12
I/O
Input/output pin for received or transmitted data
Serial communications
interface with FIFO
(SCIFA)
SCK8 to SCK11
RXD8 to RXD11
TXD8 to TXD11
I/O
Input/output pins for the clock
Input Input pins for received data
Output Output pins for transmitted data
I²C bus interface
CTS8# to CTS11#
RTS8# to RTS11#
SCL0[FM+], SCL2
Input Input pins for controlling the start of transmission and reception
Output Output pins for controlling the start of transmission and
reception
I/O
Input/output pins for clocks. Bus can be directly driven by the N-
channel open drain
SDA0[FM+], SDA2
I/O
Input/output pins for data. Bus can be directly driven by the N-
channel open drain
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 22 of 228