RX71M_15 Datasheet, PDF (171/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
5.3.6
EXDMAC Timing
5. Electrical Characteristics
Table 5.22 EXDMAC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
ICLK = 8 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
EXDMAC
Item
EDREQ setup time
EDREQ hold time
EDACK delay time
Symbol
t_EDRQS
t_EDRQH
t_EDACD
Min.
13
2
—
Max.
—
—
13
Unit
Test
Conditions
ns Figure 5.30
ns
ns Figure 5.31,
Figure 5.32
BCLK pin
EDREQ0,
EDREQ1
t_EDRQS t_EDRQH
Figure 5.30 EDREQ0 and EDREQ1 Input Timing
BCLK pin
EDACK0,
EDACK1
t_EDACD
t_EDACD
Figure 5.31 EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 171 of 228