RX71M_15 Datasheet, PDF (129/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (57 / 67)
Address
Module
Symbol Register Name
Register
Symbol
000C 4CA4h EPTPC Master Clock ID Register
1
MTCIDL
000C 4CA8h EPTPC Master Clock Port Number Register
1
MTPID
000C 4CC0h EPTPC SYNFP Transmission Interval Setting Register
1
SYTLIR
000C 4CC4h EPTPC SYNFP Received logMessageInterval Value
1
Indication Register
SYRLIR
000C 4CC8h EPTPC offsetFromMaster Value Register
1
OFMRU
000C 4CCCh EPTPC offsetFromMaster Value Register
1
OFMRL
000C 4CD0h EPTPC meanPathDelay Value Register
1
MPDRU
000C 4CD4h EPTPC meanPathDelay Value Register
1
MPDRL
000C 4CE0h EPTPC grandmasterPriority Field Setting Register
1
GMPR
000C 4CE4h EPTPC grandmasterClockQuality Field Setting Register
1
GMCQR
000C 4CE8h EPTPC grandmasterIdentity Field Setting Registers
1
GMIDRU
000C 4CECh EPTPC grandmasterIdentity Field Setting Registers
1
GMIDRL
000C 4CF0h EPTPC currentUtcOffset/timeSource Field Setting Register CUOTSR
1
000C 4CF4h EPTPC stepsRemoved Field Setting Register
1
SRR
000C 4D00h EPTPC PTP-primary Message Destination MAC Address
1
Setting Registers
PPMACRU
000C 4D04h EPTPC PTP-primary Message Destination MAC Address
1
Setting Registers
PPMACRL
000C 4D08h EPTPC PTP-pdelay Message MAC Address Setting Registers PDMACRU
1
000C 4D0Ch EPTPC PTP-pdelay Message MAC Address Setting Registers PDMACRL
1
000C 4D10h EPTPC PTP Message EtherType Setting Register
1
PETYPER
000C 4D20h EPTPC PTP-primary Message Destination IP Address Setting PPIPR
1
Register
000C 4D24h EPTPC PTP-pdelay Message Destination IP Address Setting PDIPR
1
Register
000C 4D28h EPTPC PTP event Message TOS Setting Register
1
PETOSR
000C 4D2Ch EPTPC PTP general Message TOS Setting Register
1
PGTOSR
000C 4D30h EPTPC PTP-primary Message TTL Setting Register
1
PPTTLR
000C 4D34h EPTPC PTP-pdelay Message TTL Setting Register
1
PDTTLR
000C 4D38h EPTPC PTP event Message UDP Destination Port Number PEUDPR
1
Setting Register
000C 4D3Ch EPTPC PTP general Message UDP Destination Port Number PGUDPR
1
Setting Register
000C 4D40h EPTPC Frame Reception Filter Setting Register
1
FFLTR
000C 4D60h EPTPC Frame Reception Filter MAC Address 0 Setting
1
Registers
FMAC0RU
000C 4D64h EPTPC Frame Reception Filter MAC Address 0 Setting
1
Registers
FMAC0RL
000C 4D68h EPTPC Frame Reception Filter MAC Address 1 Setting
1
Registers
FMAC1RU
Number of Access Cycles
Number Access
of Bits Size ICLK PCLK ICLK  PCLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
32
32
9 to 211 PCLKA
2 to 106 ICLK
Related
Function
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
EPTPCa
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 129 of 228