RX71M_15 Datasheet, PDF (192/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
5. Electrical Characteristics
Table 5.38 Serial Sound Interface Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
SSI AUDIO_CLK input frequency
Output clock cycle
Input clock cycle
Clock high level
Clock low level
Clock rising time
Data delay time
Setup time
Hold time
WS change edge SSIDATA output delay
Symbol
t_AUDIO
t_O
t_I
t_HC
t_LC
t_RC
t_DTR
t_SR
t_HTR
t_DTRW
Min.
Max.
Unit
Test
Conditions
—
50
MHz
150
64000
ns
Figure 5.57
150
64000
ns
60
—
ns
60
—
ns
—
25
ns
–5
25
ns
Figure 5.58,
25
—
ns
Figure 5.59
25
—
ns
—
25
ns
Figure 5.60
t_HC
SSISCKn
Figure 5.57 Clock Input/Output Timing
t_RC
t_LC
t_I, t_O
SSISCKn
(input or output)
SSIWSn, SSIDATAn,
SSIRXDn (input)
SSIWSn, SSIDATAn,
SSITXDn (output)
t_SR
t_HTR
t_DTR
Figure 5.58 Transmit/Receive Timing (SSISCKn Rising Synchronous)
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 192 of 228