RX71M_15 Datasheet, PDF (176/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
5. Electrical Characteristics
Table 5.27 MTU3 Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
Symbol
Min.
MTU3
Input capture input pulse
Single-edge
t_MTICW
1.5
width
setting
Both-edge
2.5
setting
Timer clock pulse width
Single-edge
t_MTCKWH,
1.5
setting
t_MTCKWL
Both-edge
2.5
setting
Phase counting
2.5
mode
Note 1. t_PAcyc: PCLKA cycle
Max.
—
—
—
—
—
Unit*¹
t_PAcyc
Test
Conditions
Figure 5.38
t_PAcyc Figure 5.39
PCLKA
Input capture
input
Figure 5.38 MTU3 Input Capture Input Timing
t_MTICW
PCLKA
MTCLKA to
MTCLKD
t_MTCKWL
Figure 5.39 MTU3 Clock Input Timing
t_MTCKWH
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 176 of 228