RX71M_15 Datasheet, PDF (139/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (67 / 67)
Address
Module
Symbol Register Name
Register
Symbol
Number of Access Cycles
Number Access
of Bits Size ICLK PCLK ICLK  PCLK
Related
Function
000D 0564h USBA Deep Standby USB Suspend/Resume Interrupt
Register
DPUSR1R
32
32
(3 + BUSWAIT) Rounded up to USBAa
PCLKA or more _{the nearest}
integer greater
than 1 + (3 +
BUSWAIT) ×
(frequency ratio of
ICLK/PCLKB)*⁵
Note 1. When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address
is 0008 81ECh. When different output
triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 0008 81EEh and 0008 81ECh,
respectively.
Note 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address
is 0008 81EDh. When different output
triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 0008 81EFh and 0008 81EDh,
respectively.
Note 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address
is 0008 81FCh. When different output
triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 0008 81FEh and 0008 81FCh,
respectively.
Note 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address
is 0008 81FDh. When different output
triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 0008 81FFh and 0008 81FDh,
respectively.
Note 5. When the register is accessed while the USB is operating, a delay may be generated in accessing.
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 139 of 228