RX71M_15 Datasheet, PDF (2/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2,
Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1/10)
Classification Module/Function
CPU
CPU
Memory
FPU
Code flash memory
Data flash memory
RAM
RAM with ECC
Standby RAM
Description
 Maximum operating frequency: 240 MHz
 32-bit RX CPU (RXv2)
 Minimum instruction execution time: One instruction per state (cycle of the system
clock)
 Address space: 4-Gbyte linear
 Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
 Basic instructions: 75
 Floating-point instructions: 11
 DSP instructions: 23
 Addressing modes: 11
 Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
 On-chip 32-bit multiplier: 32 × 32 → 64 bits
 On-chip divider: 32 / 32 → 32 bits
 Barrel shifter: 32 bits
 Single precision (32-bit) floating point
 Data types and floating-point exceptions in conformance with the IEEE754 standard
 Capacity: 2 Mbytes, 2.5 Mbytes, 3 Mbytes, 4 Mbytes
 No-wait access at up to 120 MHz, single wait access at frequencies above 120 MHz
 No-wait access to instructions and operands when the AFU is hit in operation at 240
MHz
 On-board programming: Four types
 Off-board programming (parallel programmer mode)
 The trusted memory (TM) function protects against the reading of programs from blocks
8 and 9.
 Capacity: 64 Kbytes
 Programming/erasing: 100,000 times
 Capacity: 512 Kbytes
 0000 0000h to 0003 FFFFh (256 Kbytes): 240 MHz No-wait access
0004 0000h to 0007 FFFFh (256 Kbytes): No-wait access at up to 120 MHz, single wait
access at frequencies above 120 MHz
 Capacity: 32 Kbytes
 Single wait access at up to 120 MHz, two wait accesses for reading and three wait
accesses for writing at frequencies above 120 MHz
 SEC-DED (single error correction/double error detection)
 Capacity: 8 Kbytes
 Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
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