RX71M_15 Datasheet, PDF (200/228 Pages) Renesas Technology Corp – Renesas MCUs

RX71M Group
5. Electrical Characteristics
Table 5.41 PDC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
PDC
PIXCLK input cycle time
PIXCLK input high pulse width
PIXCLK input low pulse width
PIXCLK rising time
PIXCLK falling time
PCKO output cycle time
PCKO output high pulse width
PCKO output low pulse width
PCKO rising time
PCKO falling time
VSYNV/HSYNC input setup time
VSYNV/HSYNC input hold time
PIXD input setup time
PIXD input hold time
Note 1. t_PBcyc: PCLKB cycle
Symbol
t_PIXcyc
t_PIXH
t_PIXL
t_PIXr
t_PIXf
t_PCKcyc
t_PCKH
t_PCKL
t_PCKr
t_PCKf
t_SYNCS
t_SYNCH
t_PIXDS
t_PIXDH
Min.*¹
37
10
10
—
—
2 × t_PBcyc
(t_PCKcyc – t_PCKr – t_PCKf)/2 – 3
(t_PCKcyc – t_PCKr – t_PCKf)/2 – 3
—
—
10
5
10
5
Max.
—
—
—
5
5
—
—
—
5
5
—
—
—
—
Unit
Test
Conditions
ns Figure 5.72
ns
ns
ns
ns
ns Figure 5.73
ns
ns
ns
ns
ns Figure 5.74
ns
ns
ns
PIXCLK input
tPIXH
tPIXcyc
tPIXf
tPIXL
tPIXr
Figure 5.72 PDC Input Clock Timing
PCKO pin output
tPCKH
tPCKcyc
tPCKf
tPCKL
tPCKr
Figure 5.73 PDC Output Clock Timing
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 200 of 228