CLRC663 Datasheet, PDF (99/132 Pages) NXP Semiconductors – Contactless reader IC

NXP Semiconductors
CLRC663
Contactless reader IC
Table 175. PLLDiv_Out bits
Bit
Symbol
Description
7 to 0 PLLDiv_Out PLL output divider factor; Refer to Section 8.8.2
Table 176. Setting for the output divider ratio PLLDiv_Out [7:0]
Value
Division
0
RFU
1
RFU
2
RFU
3
RFU
4
RFU
5
RFU
6
RFU
7
RFU
8
8
9
9
10
10
...
...
253
253
254
254
9.14 Low-power card detection configuration registers
The LPCD registers contain the settings for the low-power card detection. The setting for
LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers
LPCD_QMin, LPCD_QMax and LPCD_IMin each.
9.14.1 LPCD_QMin
Table 177. LPCD_QMin register (address 3Fh)
Bit
7
6
5
Symbol LPCD_IMax.5 LPCD_IMax.4
Access
r/w
r/w
rights
4
3
2
1
0
LPCD_QMin
r/w
Table 178. LPCD_QMin bits
Bit
Symbol
Description
7, 6
LPCD_IMax Defines the highest two bits of the higher border for the LPCD. If the
measurement value of the I channel is higher than LPCD_IMax, a
LPCD interrupt request is indicated by bit IRQ0.LPCDIrq
5 to 0
LPCD_QMin
Defines the lower border for the LPCD. If the measurement value of
the Q channel is higher than LPCD_QMin, a LPCDinterrupt request is
indicated by bit IRQ0.LPCDIrq
CLRC663
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 3 April 2012
171133
© NXP B.V. 2012. All rights reserved.
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