CLRC663 Datasheet, PDF (28/132 Pages) NXP Semiconductors – Contactless reader IC

NXP Semiconductors
CLRC663
Contactless reader IC
In order to support a fast FIFO data transfer, the address pointer is not incremented
automatically in case the address is pointing to the FIFO.
The read/write bit shall be set to logic 1.
Write Cycle
SA
I2C slave address
A7-A0
0
(W) ^Ack
0
CLRC663 register
address A6-A0
Ack
[0..n]
DATA
[7..0]
Ack
SO
Read Cycle
SA
I2C slave address
A7-A0
0
(W) ^Ack
0
CLRC663 register
address A6-A0
Ack
SO
Optional, if the previous access was on the same register address
SA
sent by master
I2C slave address
A7-A0
1
(R) ^Ack
[0..n]
sent by slave
0..n
DATA
[7..0]
Ack
DATA
[7..0]
Nack
SO
001aam305
Fig 22. Register read and write access
8.4.4.9
I²CL-bus interface
The CLRC663 provides an interface option according to of a logical handling of an I²C
interface. This logical interface fulfills the I²C specification, but the rise/fall timings will not
be according the I²C standard. Standard I/O pads are used for communication and the
communication speed is limited to 5 MBaud. The protocol itself is equivalent to the fast
mode protocol of I²C. The address is 01010xxb, where the last two bits of the address can
be defined by the application. The definition of this bits can be done by two options. With a
pin, where the higher bit is fixed to 0 or the configuration can be defined via EEPROM.
Refer to the EEPROM configuration in Section 8.7.
Table 24. Timing parameter I²CL
Parameter
Min
f_SCL
0
t_HD;STA
80
t_LOW
100
t_HIGH
100
Max
5
-
-
-
Unit
MHz
ns
ns
ns
CLRC663
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 3 April 2012
171133
© NXP B.V. 2012. All rights reserved.
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