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CLRC663 Datasheet, PDF (67/132 Pages) NXP Semiconductors – Contactless reader IC
NXP Semiconductors
CLRC663
Contactless reader IC
9.5.1 IRQ0 register
Interrupt request register 0.
Table 59. IRQ0 register (address 06h); reset value: 00h
Bit
7
6
5
4
Symbol
Set
Hi AlertIrq Lo AlertIrq IdleIrq
Access
w
rights
dy
dy
dy
3
TxIrq
dy
2
RxIrq
dy
1
ErrIrq
dy
0
RxSOF
Irq
dy
Table 60. IRQ0 bits
Bit
Symbol Description
7
Set
1: writing a 1 to a bit position 6..0 sets the interrupt request
0: Writing a 1 to a bit position 6..0 clears the interrupt request
6
HiAlerIrq Set, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert,
HiAlertIrq stores this event and can only be reset if Set is cleared.
5
LoAlertIrq Set, when bit LoAlert in register Status1 is set. In opposition to LoAlert,
LoAlertIrq stores this event and can only be reset if Set is cleared
4
IdleIrq
Set, when a command terminates by itself e.g. when the Command changes
its value from any command to the Idle command. If an unknown command
is started, the Command changes its content to the idle state and the bit
IdleIRq is set. Starting the Idle command by the Controller does not set bit
IdleIRq.
3
TxIrq
Set, when data transmission is completed, which is immediately after the last
bit is sent.
2
RxIrq
Set, when the receiver detects the end of a data stream.
Note: This flag is no indication that the received data stream is correct. The
error flags have to be evaluated to get the status of the reception.
1
ErrIrq
Set, when the one of the following errors is set:
FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr
0
RxSOFlrq Set, when a SOF or a subcarrier is detected
9.5.2 IRQ1 register
Interrupt request register 1.
Table 61. IRQ1 register (address 07h)
Bit
7
6
5
Symbol
Set
GlobalIrq LPCD_Irq
Access
w
rights
dy
dy
4
Timer4Irq
dy
3
Timer3Irq
dy
2
Timer2Irq
dy
1
Timer1Irq
dy
0
Timer0Irq
dy
CLRC663
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 3 April 2012
171133
© NXP B.V. 2012. All rights reserved.
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