CLRC663 Datasheet, PDF (27/132 Pages) NXP Semiconductors – Contactless reader IC

NXP Semiconductors
CLRC663
Contactless reader IC
Alternatively the I²C address can be configured in the EEPROM. Several address
numbers are reserved for this purpose. During device configuration, the designer has to
ensure, that no collision with these reserved addresses in the system is possible. Check
the corresponding I²C specification for a complete list of reserved addresses.
For all CLRC663 devices the upper 5 bits of the device bus address are reserved by NXP
and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address can be
freely configured by the customer in order to prevent collisions with other I²C devices by
using the interface pins (refer to Table 14) or the value of the I²C address EEPROM
register (refer to Table 34).
MSB
LSB
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
slave address
001aam304
Fig 21. First byte following the START procedure
8.4.4.7 I²C-register write access
To write data from the host controller via I²C to a specific register of the CLRC663 the
following frame format shall be used.
The first byte of a frame indicates the device address according to the I²C rules. The
second byte indicates the register address followed by up to n-data bytes. In case the
address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register
address. This enables for example a fast FIFO access. For any other address, the
address pointer is incremented automatically and data is written to the locations [address],
[address+1], [address+2]... [address+(n-1)]
The read/write bit shall be set to logic 0.
8.4.4.8 I²C-register read access
To read out data from a specific register address of the CLRC663 the host controller shall
use the procedure:
First a write access to the specific register address has to be performed as indicated in the
following frame:
The first byte of a frame indicates the device address according to the I²C rules. The
second byte indicates the register address. No data bytes are added.
The read/write bit shall be logic 0.
Having performed this write access, the read access starts. The host sends the device
address of the CLRC663. As an answer to this device address the CLRC663 responds
with the content of the addressed register. In one frame n-data bytes could be read using
the same register address. The address pointing to the register is incremented
automatically (exception: FIFO register address is not incremented automatically). This
enables a fast transfer of register content. The address pointer is incremented
automatically and data is read from the locations [address], [address+1], [address+2]...
[address+(n-1)]
CLRC663
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 3 April 2012
171133
© NXP B.V. 2012. All rights reserved.
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