CLRC663 Datasheet, PDF (26/132 Pages) NXP Semiconductors – Contactless reader IC

NXP Semiconductors
CLRC663
Contactless reader IC
8.4.4.5 I²C Acknowledge
An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or a
repeated START (Sr) condition to start a new transfer.
A master-receiver shall indicate the end of data to the slave- transmitter by not generating
an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
shall release the data line to allow the master to generate a STOP (P) or repeated START
(Sr) condition.
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVERER
SCL FROM
MASTER
1
2
S
START
condition
Fig 19. Acknowledge on the I²C- bus
not acknowledge
acknowledge
8
9
clock pulse for
acknowledgement
001aam302
P
MSB
S
1
2
or
Sr
acknowledgement
signal from slave
byte complete,
interrupt within slave
clock line held low while
interrupts are serviced
acknowledgement Sr
signal from receiver
7
8
9
ACK
1
2
3-8
9
ACK
Sr
or
P
001aam303
Fig 20. Data transfer on the I²C- bus
8.4.4.6 I²C 7-bit addressing
During the I²C-bus addressing procedure, the first byte after the START condition is used
to determine which slave will be selected by the master.
CLRC663
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 3 April 2012
171133
© NXP B.V. 2012. All rights reserved.
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