UM10562 Datasheet, PDF (94/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.11 Interrupt Priority Register 0
The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 62. Interrupt Priority Register 0
Bit Name
Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_WDT
Watchdog Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_TIMER0
Timer 0 interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_TIMER1
Timer 1 interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_TIMER2
Timer 2 interrupt priority. See functional description for bits 7-3.
5.5.12 Interrupt Priority Register 1
The IPR1 register controls the priority of the second group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 63. Interrupt Priority Register 1
Bit Name
Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_TIMER3
Timer 3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_UART0
UART0 interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_UART1
UART1 interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_UART2
UART2 interrupt priority. See functional description for bits 7-3.
5.5.13 Interrupt Priority Register 2
The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 64. Interrupt Priority Register 2
Bit Name
Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_UART3
UART3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_PWM1
PWM1 interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_I2C0
I²C0 interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_I2C1
I²C1 interrupt priority. See functional description for bits 7-3.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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