UM10562 Datasheet, PDF (785/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 30: LPC408x/407x Event Monitor/Recorder
30.6.1 Event Monitor/Recorder Control Register
The Event Monitor/Recorder Control Register allows setup of the Event Monitor/Recorder
and individual control over aspects of each channel’s operation.
Table 659. Event Monitor/Recorder Control Register (ERCONTROL - 0x4002 4084) bit description
Bit Symbol
Value Description
Reset
value
0
INTWAKE_EN0
Interrupt and wake-up enable for channel 0.
0
0 No interrupt or wake-up will be generated by event channel 0.
1 An event in channel 0 will trigger an (RTC) interrupt and a wake-up request.
1
GPCLEAR_EN0
Enables automatically clearing the RTC general purpose registers when an event 0
occurs on channel 0.
0 Channel 0 has no influence on the general purpose registers.
1 An event in channel 0 will clear the general purpose registers asynchronously.
2
POL0
Selects the polarity of an event on input pin RTC_EV0.
0
0 A channel 0 event is defined as a negative edge on RTC_EV0.
1 A channel 0 event is defined as a positive edge on RTC_EV0.
3
EV0_INPUT_EN
Event enable control for channel 0.^[1]
0
0 Event 0 input is disabled and forced high internally.
1 Event 0 input is enabled.
9:4 -
Reserved. Read value is undefined, only zero should be written.
NA
10 INTWAKE_EN1
Interrupt and wake-up enable for channel 1.
0
0 No interrupt or wake-up will be generated by event channel 1.
1 An event in channel 1 will trigger an (RTC) interrupt and a wake-up request.
11 GPCLEAR_EN1
Enables automatically clearing the RTC general purpose registers when an event 0
occurs on channel 1.
0 Channel 1 has no influence on the general purpose registers.
1 A n event in channel 1 will clear the general purpose registers asynchronously.
12 POL1
Selects the polarity of an event on input pin RTC_EV1.
0
0 A channel 1 event is defined as a negative edge on RTC_EV1.
1 A channel 1 event is defined as a positive edge on RTC_EV1.
13 EV1_INPUT_EN
Event enable control for channel 1.^[1]
0
0 Event 1 input is disabled and forced high internally.
1 Event 1 input is enabled.
19:14 -
Reserved. Read value is undefined, only zero should be written.
NA
20 INTWAKE_EN2
Interrupt and wake-up enable for channel 2.
0 No interrupt or wake-up will be generated by event channel 2.
1 An event in channel 2 will trigger an (RTC) interrupt and a wake-up request.
21 GPCLEAR_EN2
Enables automatically clearing the RTC general purpose registers when an event 0
occurs on channel 2.
0 Channel 2 has no influence on the general purpose registers.
1 An event in channel 2 will clear the general purpose registers asynchronously.
UM10562
User manual
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Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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