UM10562 Datasheet, PDF (364/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 12: LPC408x/407x USB device controller
12.12.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1
byte)
Commands 0x40 to 0x5F are identical to their Select Endpoint equivalents, with the
following differences:
• They clear the bit corresponding to the endpoint in the EpIntSt register.
• In case of a control OUT endpoint, they clear the STP and PO bits in the
corresponding Select Endpoint Register.
• Reading one byte is obligatory.
Remark: This command may be invoked by using the CmdCode and CmdData registers,
or by setting the corresponding bit in EpIntClr. For ease of use, using the EpIntClr register
is recommended.
12.12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte
(optional))
The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The
Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical
endpoint number in hex. Not all bits can be set for all types of endpoints.
Table 305. Set Endpoint Status command bit description
Bit Symbol Value Description
Reset value
0 ST
Stalled endpoint bit. A Stalled control endpoint is automatically unstalled when it
0
receives a SETUP token, regardless of the content of the packet. If the endpoint
should stay in its stalled state, the CPU can stall it again by setting this bit. When a
stalled endpoint is unstalled - either by the Set Endpoint Status command or by
receiving a SETUP token - it is also re-initialized. This flushes the buffer: in case of an
OUT buffer it waits for a DATA 0 PID; in case of an IN buffer it writes a DATA 0 PID.
There is no change of the interrupt status of the endpoint. When already unstalled,
writing a zero to this bit initializes the endpoint. When an endpoint is stalled by the
Set Endpoint Status command, it is also re-initialized.
0 The endpoint is unstalled.
1 The endpoint is stalled.
4:1 -
Reserved. Read value is undefined, only zero should be written.
NA
5 DA
Disabled endpoint bit.
0
0 The endpoint is enabled.
1 The endpoint is disabled.
6 RF_MO
Rate Feedback Mode.
0
0 Interrupt endpoint is in the Toggle mode.
1 Interrupt endpoint is in the Rate Feedback mode. This means that transfer takes
place without data toggle bit.
7 CND_ST
Conditional Stall bit.
0
0 Unstalls both control endpoints.
1 Stall both control endpoints, unless the STP bit is set in the Select Endpoint register.
It is defined only for control OUT endpoints.
UM10562
User manual
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Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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