UM10562 Datasheet, PDF (628/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 22: LPC408x/407x I2C-bus interfaces
Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).
22.8.5.1 Interrupt in Monitor mode
All interrupts will occur as normal when the module is in monitor mode. This means that
the first interrupt will occur when an address-match is detected (any address received if
the MATCH_ALL bit is set, otherwise an address matching one of the four address
registers).
Subsequent to an address-match detection, interrupts will be generated after each data
byte is received for a slave-write transfer, or after each byte that the module believes it
has transmitted for a slave-read transfer. In this second case, the data register will actually
contain data transmitted by some other slave on the bus which was actually addressed by
the master.
Following all of these interrupts, the processor may read the data register to see what was
actually transmitted on the bus.
22.8.5.2 Loss of arbitration in Monitor mode
In monitor mode, the I²C module will not be able to respond to a request for information by
the bus master or issue an ACK. Some other slave on the bus will respond instead.
Software should be aware of the fact that the module is in monitor mode and should not
respond to any loss of arbitration state that is detected.
22.8.6 I²C Data buffer register
In monitor mode, the I²C module may lose the ability to stretch the clock if the ENA_SCL
bit is not set. This means that the processor will have a limited amount of time to read the
contents of the data received on the bus. If the processor reads the I2DAT shift register, as
it ordinarily would, it could have only one bit-time to respond to the interrupt before the
received data is overwritten by new data.
To give the processor more time to respond, a new 8-bit, read-only I2DATA_BUFFER
register has been added. The contents of the 8 MSBs of the I2DAT shift register are
transferred to the I2DATA_BUFFER automatically after every 9 bits (8 bits of data plus
ACK or NACK) has been received on the bus. This means that the processor will have 9
bit transmission times to respond to the interrupt and read the data before it is overwritten.
The processor will still have the ability to read I2DAT directly, as usual, and the behavior of
I2DAT will not be altered in any way.
Although the I2DATA_BUFFER register is primarily intended for use in monitor mode with
the ENA_SCL bit = ‘0’, it is available for reading at any time under any mode of operation.
Table 497. I²C Data buffer register (DATA_BUFFER - addresses 0x4001 C02C (I2C0),
0x4005 C02C (I2C1), 0x400A 002C (I2C2)) bit description
Bit Symbol Description
Reset
value
7:0 Data This register holds contents of the 8 MSBs of the I2DAT shift register.
0
31:8 -
Reserved. The value read from a reserved bit is not defined.
NA
UM10562
User manual
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Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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