UM10562 Datasheet, PDF (79/942 Pages) NXP Semiconductors – LPC408x/407x User manual

UM10562
Chapter 5: LPC408x/407x Nested Vectored Interrupt
Controller (NVIC)
Rev. 1 — 13 September 2012
User manual
5.1 Features
• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M4
• Tightly coupled interrupt controller provides low interrupt latency
• Controls system exceptions and peripheral interrupts
• The NVIC supports 40 vectored interrupts in these devices
• 32 programmable interrupt priority levels, with hardware priority level masking
• Relocatable vector table
• Non-Maskable Interrupt
• Software interrupt generation
5.2 Description
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M4. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts. The NVIC handles interrupts in addition to system exceptions.
Exceptions include Reset, NMI, Hard Fault, MemManage Fault, Bus Fault, Usage Fault,
SVCall, Debug Monitor, PendSV, and Systick.
See the ARM Cortex-M4 User Guide referred to in Section 40.1 for details of NVIC
operation.
5.3 Interrupt sources
Table 50 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source, as noted.
Exception numbers relate to where entries are stored in the exception vector table.
Interrupt numbers are used in some other contexts, such as software interrupts.
Note that system exceptions are hard-wired into the Cortex-M4 and are not shown in the
table. Some other information about the Systick interrupt can be found in the System Tick
Timer chapter, Section 25.1
In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to
operate from an external signal, the NMI function must be connected to the related device
pin (P2[10] / EINT0n / NMI). When connected, a logic 1 on the pin will cause the NMI to be
processed. For details, refer to the Cortex-M4 User Guide that is an appendix to this User
Manual.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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