UM10562 Datasheet, PDF (82/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
Table 50. Connection of interrupt sources to the Vectored Interrupt Controller
Interrupt Exception Vector Function
ID
Number Offset
Flag(s)
36
52
0xD0 SSP2
Tx FIFO half empty of SSP2
Rx FIFO half full of SSP2
Rx Timeout of SSP2
Rx Overrun of SSP2
37
53
0xD4 LCD controller
BER, VCompI, LNBUI, FUFI, CrsrI
38
54
0xD8 GPIO interrupts
P0xREI, P2xREI, P0xFEI, P2xFEI
39
55
0xDC PWM0
Match 0 - 6 of PWM0
Capture 0-1 of PWM0
40
56
0xE0 EEPROM
EE_PROG_DONE, EE_RW_DONE
5.4 Vector table remapping
The Cortex-M4 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register (VTOR) contained in the Cortex-M4.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M4 address
space. The vector table should be located on a 256 word (1024 byte) boundary to insure
alignment. See the ARM Cortex-M4 User Guide referred to in Section 40.1 for details of
the Vector Table Offset feature.
ARM describes bit 29 of the VTOR (TBLOFF) as selecting a memory region, either code
or SRAM. For simplicity, this bit can be thought as simply part of the address offset since
the split between the “code” space and the “SRAM” space occurs at the location
corresponding to bit 29 in a memory address.
Examples:
To place the vector table at the beginning of the Main SRAM, starting at address
0x1000 0000, place the value 0x1000 0000 in the VTOR register. This indicates address
0x1000 0000 in the code space, since bit 29 of the VTOR equals 0.
To place the vector table at the beginning of the peripheral SRAM, starting at address
0x2000 0000, place the value 0x2000 0000 in the VTOR register. This indicates address
0x2000 0000 in the SRAM space, since bit 29 of the VTOR equals 1.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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