UM10562 Datasheet, PDF (206/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 10: LPC408x/407x Ethernet
Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block.
Receive flow control frames are automatically handled by the MAC. Transmit flow control
frames can be initiated by software. In half duplex mode, the flow control module will
generate back pressure by sending out continuous preamble only, interrupted by pauses
to prevent the jabber limit from being exceeded.
The Ethernet block has both a standard Media Independent Interface (MII) bus and a
Reduced Media Independent Interface (RMII) to connect to an external Ethernet PHY
chip. MII or RMII mode can be selected by the RMII bit in the Command register. The
standard nibble-wide MII interface allows a low speed data connection to the PHY chip:
2.5 MHz at 10 Mbps or 25 MHz at 100 Mbps. The RMII interface allows a low pin count
double clock data connection to the PHY. Registers in the PHY chip are accessed via the
AHB interface through the serial management connection of the MIIM bus, typically
operating at 2.5 MHz.
10.8.2 Example PHY Devices
Some examples of compatible PHY devices are shown in Table 144.
Table 144. Example PHY Devices
Manufacturer
Part Numbers
Broadcom
BCM5221
ICS
ICS1893
Intel
LXT971A
LSI Logic
L80223, L80225, L80227
Micrel
KS8721
National
DP83847, DP83846, DP83843
SMSC
LAN83C185
UM10562
User manual
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Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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